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Technology Corporation
ATXP5
Jumper Free Over Clock Controller Datasheet
Release Date: Jan. 2005
Revision: 1.0
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Revision History
Version
1.0
ATXP5 V1.0
Jumper Free Over Clock Controller
Date
Jan/19/2005
Changes from Last Version
Add "Ordering Information" about green device description
Technology Corporation
ATXP5 V1.0
Jumper Free Over Clock Controller
Table of Contents
1. General Description.............................................................................. 1 2. Features............................................................................................ 1 3. Package Configuration.......................................................................... 2 4. Pin Description.................................................................................... 3 5. Configuration Registers.......................................................................... 5 6. Package Information............................................................................. 8
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ATXP5 V1.0
Jumper Free Over Clock Controller
Figures
Figures 1. ATXP5 Pin Diagram (Top View)................................................... 2
Tables
Table 1. Pin Description Table......................................................................... 3
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1. General Description
ATXP5 V1.0
Jumper Free Over Clock Controller
ATXP5 is a full feature of over clocking device. It integrates all functions that are possible to be utilized for over-clocking purpose.
2. Features
Provide Four FID Input (FIDIN0-3) and Eight Output Pins (FIDOCS0-3 & FIDOCPU0-3) - FIDCS0-3 Outputs for Chip Set & FIDCPU0-3 Outputs for CPU Provide NBPWROK pin Provide Five GPIO Pins Support Auto-Recover - Build-in Watch Dog Timer & Reset Output Signal Pin Provide CPU Changing Detect Pin (SLOTOCC#) SM Bus Interface Package: SSOP 28-Pin
1 Specification Subject to Change without Notice.
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ATXP5 V1.0
Jumper Free Over Clock Controller
3. Pin Configuration
3VSB G PIO 0 G PIO 1 CPUPW ROK FIDIN0 FIDIN1 FIDIN2 FIDIN3 NB_PW ROK SDA SCL RSTOUT# G ND SLO TOCC#
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25
TEST/ASEL GPIO 2 GPIO 3 GPIO 4 FIDCS0 FIDCS1 FIDCS2 FIDCS3 LEVEL FIDCPU0 FIDCPU1 FIDCPU2 FIDCUP3 VBAT
A T X P 5
24 23 22 21 20 19 18 17 16 15
Figure 1. ATXP5 Pin Diagram (Top View)
Ordering Information ATXP5- Commercial Standard ATXP5G- Green Device with Commercial Standard
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4. Pin Description
ATXP5 V1.0
Jumper Free Over Clock Controller
I/O TYPE DESCRIPTION ---- TTL level input. INt ---- TTL level input with Schmitt-trigger. INts INt-10k-up ---- TTL level input l pin with 12mA drive/sink current and10K ohm pull-up resistor. INt-47k-up ---- TTL level input l pin with 12mA drive/sink current and47K ohm pull-up resistor. OD12 ---- Open-drain with 12mA sink current. ---- Output buffer with 12mA drive/sink current O12 I/OD12 ---- TTL level bi-directional pin, and open-drain output with 12mA sink current. ---- TTL level bi-directional pin, and output with 12mA drive/sink current. I/O12
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Pin name 3VSB GPIO0 GPIO1 CPUPWROK FIDIN0 FIDIN1 FIDIN2 FIDIN3 NB_PWROK SDA SCL RSTOUT# GND SLOTOCC# VBAT FIDCPU3 FIDCPU2 FIDCPU1 FIDCPU0 LEVEL FIDCS3 FIDCS2 FIDCS1
I/O Type POWER I/O12 I/O12 INt-47k-up INtx INtx INtx INtx OD12 I/OD12 INts OD12 INts O12 O12 O12 O12 OD12 OD12 OD12
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Function Power Pin General Purpose I/O Pin General Purpose I/O Pin Receive CPUPWROK Signal form CPU Receive FID0 Signal form CPU Receive FID1 Signal form CPU Receive FID2 Signal form CPU Receive FID3 Signal form CPU North-Bridge Power-OK. SMB Data Signal SMB Clock Signal Rest Output Signal GROUND Pin Receive SLOTOCC# from CPU Power Pin FID3 Signal Output Pin to CPU FID2 Signal Output Pin to CPU FID1 Signal Output Pin to CPU FID0 Signal Output Pin to CPU Power Pin FID3 Signal Output Pin to Chip Set FID2 Signal Output Pin to Chip Set FID1 Signal Output Pin to Chip Set
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24 25 26 27 28 FIDCS0 GPIO4 GPIO3 GPIO2 Test /ASEL OD12 I/O12 I/O12 I/O12 INt-10k-up
ATXP5 V1.0
Jumper Free Over Clock Controller
FID0 Signal Output Pin to Chip Set General Purpose I/O Pin General Purpose I/O Pin General Purpose I/O Pin Test Pin/Power-Strapping Device Address Select Pin. Table1. Pin Description Table
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5. Configuration Registers
Register CPU FID Output Control Register
ATXP5 V1.0
Jumper Free Over Clock Controller
Chipset FID Output Data Register NEW CPU Status/Control / GPIO4-0 Input Enable Register Watching-Dog Timer Register
Offset Power on/Reset Description Default value 02h 00000000b <7:5> Reserved. <4> CPU/CS FID Output Enable =0 FIDIN pins pass to FIDCS and FIDCPU pins. =1 FIDCS pins are controlled by CR03 bit 3~0(CS FID) and FIDCPU pins are controlled by CR02 bit 3~0(CPU FID). <3:0> CPU FID output value. This register is reset by 3VSB, RSTOUT#, and New CPU events. 03h 00000000b <7:4> Reserved. <3:0> CS FID Output Value. This register is reset by VBAT. 05h 00000000b <7> New CPU Status <6> Clear New CPU Status. <5:0> Reserved. 07h 00000000b Watching-Dog Timer Register <7:0> Read this register means how much time left that Watching-Dog Timer will be time-out. Write this register to set a time into Watching-Dog Timer. <7> Watching-Dog Timer time-out status Register = 0 No Watching-Dog time-out event. = 1 Watching-Dog time-out event exists. Write "0" clear this status <6> Watching-Dog Timer Enable <5:4> Reserved. <3:2> Watching-Dog Timer time-unit select = 00 1 second. = 01 0.1 second. = 10 10 mini-second. = 11 1 mini-second. <1:0> RSTOUT# pulse width select = 00 1 second. = 01 0.1 second. = 10 10 mini-second. = 11 1 mini-second.
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Watching-Dog Timer Status/MISC Control Register
08h
00000000b
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GPIO4-0 Input Enable Register 09h 00000000b
ATXP5 V1.0
Jumper Free Over Clock Controller
GPIO4-0 Data Register
0Ah
111111111b
<7> Reserved. <6:3> GPIO4~1 input enable= 0 the corresponding GPIO is an output pin =1 the corresponding GPIO is an input pin. <2:1> Reserved. <0> GPIO0 input enable= 0 the corresponding GPIO0 is an output pin =1 the corresponding GPIO0 is an input pin. <7> Reserved. <6:3> GPIO4-1 data register If the GPIO pin is set as an input pin, the input value can be obtained by reading this register. If the GPIO pin is set as an output pin, the output value can be controlled by writing this register, and the output value can also be read back. <2:1>Reserved. <0> GPIO0 data register If the GPIO0 pin is set as an input pin, the input value can be obtained by reading this register. If the GPIO0 pin is set as an output pin, the output value can be controlled by writing this register, and the output value can also be read back. <7> Reserved. <6:3> GPIO4-1 output type = 0 The corresponding GPIO pin is open-drain output pin. = 1 The corresponding GPIO pin is push-pull output pin. <2:1>Reserved. <0> GPIO0 output type = 0 The corresponding GPIO0 pin is open-drain output pin. = 1 The corresponding GPIO0 pin is push-pull output pin.
GPIO4-0 Output Type Select Register
0Bh
00000000b
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6. Package Information SSOP 28 pin Outline Dimension
\
D
ATXP5 V1.0
Jumper Free Over Clock Controller
L1
2 1
0.25MM
E1
E
GAUGE PLANE
R
R1
L Detail A
h x 45
ZD
c
A2
A
C
e
B
Symbol A A1 A2 B c E D E E1 L H ZD R1 R 1 2 JEDEC
Dimension in mm Min 1.35 0.10 0.20 0.18 9.80 5.79 3.81 0.41 0.25 0.838 REF 0.20 0.20 0 0 5 10 15 8 0.33 9.91 5.99 3.91 0.635 Nom 1.63 0.15 Max 1.75 0.25 0.50 0.30 0.25 10.01 6.20 3.99 1.27 0.50
Dimension in inch Min 0.053 0.004 0.008 0.007 0.025 BASIC 0.386 0.228 0.150 0.016 0.010 0.033 REF 0.008 0.008 0 0 5 10 15 8 0.013 0.390 0.236 0.154 0.025 0.394 0.244 0.157 0.050 0.020 Nom 0.064 0.006 Max 0.069 0.010 0.059 0.012 0.010
0.635 BASIC
MO-137 (AF)
A1
0.10MM
DTEAIL A
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Copyright (c) 2001 Attansic Technology Corp. The materials contained in this document replace all previous documentation issued for the related products included herein. Please contact Attansic Technology Corp. for the latest documents. Attansic is the trademark of Attansic Technology Corp. All specifications are subject to change without notice. Additional copies of this document or other Attansic literatures may be obtained from: 3FL., No.147, Hsien Cheng 9th Rd, Chu-Pei, Hsin-Chu Hsien, Taiwan Tel: 886-3-5545660 Fax: 886-3-5545661 To find out more about Attansic, visit our World Wide Web address at: http://www.attansic.com.tw/

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